1. Field of the Invention
The present invention relates to a transistor circuit apparatus wherein a drain-source breakdown voltage of a MOS transistor is improved, thereby preventing an avalanche breakdown.
2. Description of the Related Art
It is generally known that with a bipolar transistor, if a collector-emitter voltage is applied while a base is being opened, an avalanche breakdown occurs when a voltage value reaches a certain level, and as a result a large current flows across the collector and emitter. The reason for this is that a dark current flowing across the collector and emitter causes an electron avalanche phenomenon in a base region, and an excessively large current flows. This phenomenon is stated, for example, in "Physics and Technology of Semiconductor Devices", A. S. Grove (John Wiley and Sons, Inc. 1976, pp. 231-233).
On the other hand, the inventors of the present invention have already proposed an NMOS output circuit wherein a back gate bias effect compensation was effected (Jap. Pat. Appln. KOKAI No. 5-37336).
FIGS. 1 and 2 show examples of a conventional transistor circuit apparatus. FIG. 1 shows a non-inversion type tri-state output circuit, and FIG. 2 shows a non-inversion type bi-state output circuit.
FIG. 1 shows a circuit configuration for effecting a control wherein transistors N3 and N4 are controlled by NOR circuits NOR1 and NOR2, thereby producing an output OT1 having the same phase as an input IN1 or setting the output OT1 in a high-impedance state.
In FIG. 2, transistors N3 and N4 are controlled by inverters IV1 and IV2, thereby producing an output OT1 having the same phase as an input IN. The output OT1 is pulled up to Vcc2 by a resistor R. The resistor R corresponds to a circuit 11 in FIG. 1.
For example, in the NMOS output circuit shown in FIG. 1, suppose that a power supply voltage Vcc (=Vcc1) is short-circuited to a ground potential Vss, i.e. a power supply is set in a turned-off state. In addition, suppose that an I/O bus line is supplied with a signal from the circuit 11 driven by a power supply Vcc2 which is different from Vcc1.
Specifically, the I/O bus line is shared by circuits connected to two power supply systems (Vcc=Vcc1; Vcc2).
In this case, Vcc=Vss and the gate (front gate) potentials of NMOS transistors N3, N4, N5, N61 and N62 are set at ground potential Vss. Thus, the gate-source voltage Vgs of these NMOS transistors N3, N4, N5, N61 and N62 is 0V, and these transistors are turned off. In other words, the back gates (node A) of the NMOS transistors N3 and N5 are set in a high impedance state.
Accordingly, the base of a parasitic npn bipolar transistor constituted by the drain, back gate and source of the NMOS transistor N3 shown in FIG. 1 is in the open state (i.e. at a potential in the open state).
In this state, if a signal is supplied to the I/O bus line OT1 from the circuit 11 driven by the power supply Vcc2, the aforementioned avalanche occurs when the supplied signal is at high level. The breakdown voltage at this time is determined by properties of device structure such as an impurity concentration in the base. Once the device structure is determined, improvement in breakdown voltage is difficult.
The state just after the power supply Vcc has been short-circuited to Vss will now be considered with reference to FIG. 1. The voltage at node A, which was at the Vcc level just before the short (turn-off of power supply), is changed towards the Vss level by the parasitic diode formed between the Vcc and node A. However, since the NMOS transistor N3, by which the voltage at node A is to be varied towards the Vss, is turned off, the voltage at node A does not immediately decrease below a level close to a diode forward voltage (about 0.4V).
However, after the voltage at node A reaches this level, the node voltage gradually goes to the Vss level by leak current.
On the other hand, it is not known that when a little charge remains in the gate of the NMOS transistor (i.e. node B corresponding to the gate of transistor N100 in FIG. 3), the avalanche breakdown voltage of the parasitic bipolar transistor (constituted by the source, back gate and drain) decreases, as will be described below.
FIG. 3 shows a measuring circuit using an NMOS transistor N100 the back gate (i.e. P-well substrate) of which is set in the open state. For example, by using this measuring circuit, the relationship between the drain-source voltage Vds and drain-source current Ids in the case where Vgs (=0V, 0.2V, 0.3V, 0.4V) was applied to the gate of the transistor N100 was examined. As is shown in FIG. 4, it was confirmed that the drain-source voltage Vds decreased and this fact (decrease of avalanche breakdown voltage) was confirmed.
In the employed sample of the NMOS transistor N100, threshold voltage Vth=0.6V and W/Leff=630 .mu.m/1.0 .mu.m (W=channel width; Leff=effective channel length). Symbol B1 denotes a npn bipolar transistor parasitic on the NMOS transistor N100.
FIG. 4 shows measurement results obtained with measuring circuit of FIG. 3, including temperature dependency (Ta=-40.degree., 25.degree., 85.degree. C.). As is clear from FIG. 4, the current Ids flows abruptly if the variable gate potential Vgs has reached the drain-source potential Vds in each case.
In order to prevent device destruction due to a very large current (i.e. breakdown current mentioned below), a current limit was provided at 10 .mu.A in the measurement. However, the occurrence of breakdown is clearly understood from a sudden increase in current Ids representing characteristics in this graph.
When the gate-source voltage Vgs=0V, the avalanche breakdown voltage of the bipolar transistor itself is observed. However, it is understood from the decrease in drain-source potential Vds that if Vgs&gt;0V, the breakdown voltage decreases.
FIG. 5 shows the relationship between the breakdown voltage Vds and gate potential Vgs, which was found from the measurement result as shown in FIG. 4. Specifically, when a positive gate voltage is applied to the gate of the transistor N100, the energy band structure at the semiconductor surface just below the gate and the charge distribution are changed. Consequently, a sub-threshold current flows below the gate. This current triggers an avalanche breakdown on the semiconductor surface at the lower gate voltage Vds.
In FIG. 1, the gate of transistor N3 is a common node. This, too, causes the decrease in breakdown voltage, as described below.
In FIG. 1, if a residual potential component is included in the gate potential of the transistor N5 just after the power supply Vcc was short-circuited to Vss, a sub-threshold current thereof acts as a carrier current. When the potential of the output node OT1 is raised, the sub-threshold current raises the potential of point A, i.e. P-well potential, via the source-drain path of the transistor N5 and causes an avalanche breakdown.
Thus, the avalanche breakdown voltage is lowered and the avalanche breakdown is likely to occur.
As has been described above, the avalanche breakdown voltage decreases abruptly due to a little residual potential. Thus, if one of the two power supply systems (Vcc=Vcc1, Vcc2) is turned off (i.e. Vcc=Vss), the normal operation cannot be expected.
Even if there is no residual potential, if a pulse is applied to the I/O bus line OT1, a charge is injected in the gate by a mirror capacitance created between the gate and source and between the gate and drain of the NMOS transistor N3.
Consequently, the gate potential of the transistor N3 rises, as in the case where the aforementioned residual potential is present. Accordingly, the avalanche breakdown voltage falls abruptly. Therefore, if one of the two power supply systems (Vcc=Vcc1, Vcc2) is turned off (i.e. Vcc=Vss), the normal operation cannot be expected.